Integrated circuits (ICs) are potentially exposed to electrical over-stress (EOS) events from power surges and other sources that can impact circuit reliability. During EOS events, voltage levels on conductors, or nodes, used to deliver power to circuits are substantially higher than normal voltage levels, so circuit components can be damaged. EOS concerns increase as IC dimensions shrink due to the increased vulnerability of thin oxides and low junction breakdown voltages.
Compared to transient electrostatic discharge (ESD) events with fast rise times and short durations, EOS events have slower rise times, higher energies, and/or wider ranges of pulse widths. Protecting circuits from EOS events therefore entails approaches that can differ from those used for ESD events. In most cases, ESD protection circuits are built on an IC chip to address ESD threats within all manufacturing and packaging processes, while some discrete EOS or system ESD protection elements are located outside the chip.
An EOS circuit is provided in some prior approaches by diode strings that protect sensitive circuit elements during EOS events but allow significant leakage currents during normal circuit operation. Polysilicon diodes used in some approaches need to be large to avoid significant heat generation during an EOS event.
Like reference symbols in the various drawings indicate like elements.